This application claims the benefit of Korean Application No. 72197/1996 filed Dec. 26, 1996, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a capacitor and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for suppressing a leakage current.
2. Discussion of the Related Art
To achieve high integration of semiconductor devices, various cell structures have been proposed to minimize a size of DRAM devices. Generally, in a semiconductor memory cell including a transistor and a capacitor, a signal charge is stored in a storage node of a capacitor connected to a transistor (a switching transistor). Accordingly, a size of a capacitor has a direct relationship with a size of the memory cell. As a result, the amount of charges which can be stored in the storage node is subject to be decreased with the reduced size of capacitor in highly integrated devices.
Therefore, a capacitor storage node of a memory cell requires a minimum surface area to transmit signals generated in the switching transistor without any malfunction. In other words, the storage node of the capacitor must have a relatively large surface area in a limited area of a semiconductor substrate to store large enough charges from the transistor.
Capacitors having a fin structure or a pillar structure are of interest particularly in parallel plate structured capacitors. A capacitor of a pin or pillar structure is useful to increase the its capacitance. However, the capacitor having a pillar structure has a problem of leakage current because high electric field is concentrated at a sharp edged top surface of the capacitor.
A conventional capacitor and a manufacturing method thereof will be explained in details with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view illustrating a structure of a conventional capacitor and FIGS. 2A to 2E are cross-sectional views illustrating the process steps of fabricating the conventional capacitor.
As shown in FIG. 1, an interlayer insulating layer 2 and a blocking layer 3 are formed to have the same contact hole on a predetermined portion of a substrate 1. A storage node 5a is then formed in the contact hole and on a predetermined portion of the blocking layer 3 adjacent to the contact hole. A pillar storage node 8 is formed on a peripheral portion of the surface of the storage node 5a. In this case, the pillar storage node 8 has a sharp edged top surface.
After, a plate node 10 is formed on the entire surface of a dielectric layer 9, a U-form capacitor is completed.
In a conventional method of fabricating a capacitor, an interlayer insulating layer 2 is formed on the substrate 1 using a thermal oxidation process or a chemical vapor deposition (CVD) process, as shown in FIG. 2A. Then, a blocking layer 3, for example, a nitride, is formed on the interlayer insulating layer 2. Next, a photoresist layer 4 is coated on the blocking layer 3. Subsequently, with the photoresist pattern 4 serving as a mask, an anisotropic etching process is applied to the blocking layer 3 and the interlayer insulating layer 2 to expose a predetermined portion of the substrate to form a contact hole.
Referring to FIG. 2B, the remaining photoresist layer 4 is removed and a polysilicon layer 5 is formed on the entire surface. A planar protection layer 6 is then formed on the polysilicon layer 5. For example, phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) is used for the planar protection layer 6.
Referring to FIG. 2C, another photoresist layer 7 is coated on the entire surface and then is subjected to be patterned by an exposure and development process. With the photoresist pattern 7 serving as a mask, the planar protection layer 6 is anisotropically etched to form a pillar layer 6a over the contract hole.
Referring to FIG. 2D, the remaining photoresist layer 7 is removed. Subsequently, a polysilicon layer is formed on the entire surface and then is anisotropically etched using a reactive ion etching (RIE) method to form a pillar storage node 8 surrounding the pillar layer 6a. In this process, the storage node 5a is anisotropically etched simultaneously. Next, the pillar layer 6a is removed by wet-etching. In this case, the blocking layer 3 serves to protect the interlayer insulating layer 2.
Referring to FIG. 2E, an oxide layer and a polysilicon layer are formed successively on the entire surface and then patterned to form a dielectric layer 9 and a plate node 10. Accordingly, a conventional U-form capacitor is completed.
However, the conventional capacitor and the method of fabricating the same have following problems.
First, since an electric field is concentrated on a sharp edged top surface of a pillar storage node, a leakage current is generated around the sharp edged top surface.
Second, since the height of a pillar storage node is not readily controllable, it is difficult to fabricate the capacitor having a desirable capacitance. As a result, the reproducibility of a capacitor is seriously reduced.
Accordingly, the present invention is directed to a capacitor and a method of fabricating the same that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a capacitor includes a substrate, a first insulating layer having a contact hole on the substrate, a first storage node formed in the contract hole and on the first insulting layer adjacent to the contact hole; a second storage node formed on a peripheral portion of the first storage node and having a planar top surface, a dielectric layer on surfaces of the first and second storage nodes, and a plate node formed on the dielectric node.
In another aspect of the present invention, a method of fabricating a capacitor includes the steps of providing a substrate, forming a first insulating layer having a contact hole on the substrate, forming a first conductive layer in the contact hole and on the first insulating layer, forming successively a second insulating layer and a third insulating layer which is wider than the second insulating layer on a predetermined portion of the first conductive layer, forming a second conductive layer surrounding the second insulating layer, contacting with the first conductive layer, and having its planar edged top surface, removing the second and third insulating layers, forming a dielectric layer on surfaces of the first and second conductive layers, and forming a third conductive layer on the dielectric layer.
In another aspect of the present invention, a capacitor includes a substrate, an insulating layer on the substrate, the insulting layer having a contact hole over the substrate, a first storage node in the contact hole and on the insulting layer, a second storage node on a peripheral portion of the first storage node, the second storage node having a planar top surface, a dielectric layer on surfaces of the first and second storage nodes, and a plate node on the dielectric layer.
In another aspect of the present invention, a method of fabricating a capacitor having a substrate, the method includes the steps of forming a first insulating layer on the substrate, the first insulating layer having a contact hole over the substrate, forming a first conductive layer in the contact hole and on the first insulating layer, forming a second insulating layer on a predetermined portion of the first conductive layer, forming a third insulating layer on the second insulating layer, the third insulating layer having a width wider than the second insulating layer, forming a second conductive layer surrounding the second insulating layer, the second conductive layer contacting the first conductive layer and having a planar top surface, removing the second and third insulating layers, forming a dielectric layer on surfaces of the first and second conductive layers, and forming a third conductive layer on the dielectric layer.
In another aspect of the present invention, a method of fabricating a capacitor having a substrate, the method includes the steps of forming a first insulating layer on the substrate, the first insulating layer having a contact hole over the substrate, forming a first conductive layer in the contact hole and on the first insulating layer forming a second insulating layer on a predetermined portion of the first conductive layer, forming a third insulating layer on the second insulating layer, the third insulating layer having a width narrower than the second insulating layer, forming a fourth insulating layer on the third insulating layer, the fourth insulating layer having a width wider than the third insulating layer, forming a second conductive layer surrounding the second and fourth insulating layers, the second conductive layer having a planar top surface, forming a dielectric layer on surfaces of the first and second conductive layers, and forming a third conductive layer on the dielectric layer.
In a further aspect of the present invention, a method of fabricating a capacitor having a substrate, the method includes the steps of forming a first insulating layer on the substrate, the first insulating layer having a contact hole, forming a first conductive layer in the contact hole and on the first insulating layer, forming a second insulating layer on the first conductive layer, forming a third insulating layer on the second insulating layer, the third insulating layer having a width wider than the second insulating layer, forming a second conductive layer surrounding the second insulating layer, the second conductive layer contacting the first conductive layer and having a planar top surface, removing the third insulating layer, removing the second insulating layer, removing a portion of the first insulating layer to space apart the first conductive layer from a surface of the insulating layer, forming a dielectric layer on an expose surface over the substrate, and forming a third conductive layer on the dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.